AMD Introduced SSE5 Instruction Set Extensions amd sse5 ¸í·É ÁýÇÕ È®Àå ±â´É µµÀÔ
Friday, August 31st, 2007 2007³â 8¿ù 31ÀÏ (±Ý)
AMD has just announced the new X86 SSE5 (Streaming SIMD Extensions Version 5) instruction-set extensions yesterday for its future product lines. amdÀº ÀÌÁ¦ »õ·Î¿î x86À» ¹ßÇ¥Çß´Ù sse5 (½ºÆ®¸®¹Ö simd È®Àå ¹öÀü 5) ±³À° - ¹Ì·¡ÀÇ Á¦Ç° ¶óÀÎÀ» ¼³Á¤ ¾îÁ¦ÀÇ È®ÀåÇÕ´Ï´Ù. Although the implementation will only take place in year 2009 in its next generation core, codenamed as Bulldozer, but the specification has been released to developer community now. ºñ·Ï 2009 ³â °³ÃÖ¸¦ ±¸ÇöÀÇ °æ¿ì¿¡¸¸ ´ÙÀ½ ¼¼´ë ÄÚ¾î, ÄÚµå¸íÀ¸·Î ºÒµµÀú,ÇÏÁö¸¸ Áö±ÝÀÇ »ç¾çÀÌ ¸±¸®½ºµÇ¾ú½À´Ï´Ù °³¹ßÀÚ Ä¿¹Â´ÏƼ·ÎÇÕ´Ï´Ù. This has marked a meaningful milestone for AMD in the evolution for its processor architecture ahead of its competitor, Intel when defining a new standard for the community. À̰ÍÀº Ç¥½Ã°¡¿¡ ´ëÇÑ ÀǹÌÀÖ´Â ÀÌÁ¤Ç¥ÀÇ ¹ßÀü amdÀ» ¾ÕµÎ°í °æÀï ¾÷üÀÇ ÇÁ·Î¼¼¼ ¾ÆÅ°ÅØÃ³, ÀÎÅÚ °æ¿ì Áö¿ª »çȸ¿¡ ´ëÇÑ »õ·Î¿î Ç¥ÁØÀ» Á¤ÀÇÇÕ´Ï´Ù. If you recall, Intel has came out with SSE-SSE4 extensions instruction standard for the market since Pentium III to tackle AMD¡¯s 3D Now! ¸®ÄÝÇÏ´Â °æ¿ì, ÀÎÅÚÀº ³²µ¿ - sse4 È®Àå ¸í·É¾î·Î ³ª¿Â Ç¥ÁØÀ» ÆæÆ¼¾ö 3¿¡ Á¾»ç ÀÌÈÄÀÇ ½ÃÀå amdÀÇ 3 Â÷¿øÇϼ¼¿ä! capability and now AMD seems to go to release the latest version of SSE5 ahead of Intel. ±×¸®°í Áö±Ý¿¡ °¥ ´É·Â amd º¸Àδ٠sse5 ¾ÕµÐ ÀÎÅÚÀÇ ÃֽйöÀüÀ» ¸±¸®½ºÇÕ´Ï´Ù.
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