AMD Introduced SSE5 Instruction Set Extensions
AMD has just announced the new X86 SSE5 (Streaming SIMD Extensions Version 5) instruction-set extensions yesterday for its future product lines. Although the implementation will only take place in year 2009 in its next generation core, codenamed as Bulldozer, but the specification has been released to developer community now. This has marked a meaningful milestone for AMD in the evolution for its processor architecture ahead of its competitor, Intel when defining a new standard for the community. If you recall, Intel has came out with SSE-SSE4 extensions instruction standard for the market since Pentium III to tackle AMD’s 3D Now! capability and now AMD seems to go to release the latest version of SSE5 ahead of Intel.
SSE instructions set poses a great improvement to the PC architecture performance especially when comes to power hungry processing such as graphics, multimedia and security applications. However, it will be useless if there is no software development support on this feature by software vendors. Some of the great features in this SSE5 includes fused MAC (Multiply-accumulate) instruction and 3-Operand Instructions that would greatly help in multi-cores environment.
Intel has not responded directly to the announcement but some may guess if Intel will adopt or decide to skip SSE5 by releasing SSE6 directly. Anyway, Penryn (Intel quad-core Xeon processor) which is about to be launched by end of this year will have the SSE4 enhancement only and hence, it would be too early to comment on this.
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