AMD Introduced SSE5 Instruction Set Extensions AMD´Â SSE5 ¸í·É¾î ¼¼Æ®¸¦ È®Àå ±â´É ¼Ò°³

sse5.jpg AMD has just announced the new X86 SSE5 (Streaming SIMD Extensions Version 5) instruction-set extensions yesterday for its future product lines. AMD´Â ´ÜÁö (½ºÆ®¸®¹Ö SIMD È®Àå ¹öÀü 5) - È®Àå ¸í·É¾î ¼¼Æ® ¾îÁ¦ÀÇ ¹Ì·¡¿¡ ´ëÇÑ »õ·Î¿î x86 SSE5 Á¦Ç° ¶óÀÎÀ» ¹ßÇ¥Çß´Ù. Although the implementation will only take place in year 2009 in its next generation core, codenamed as Bulldozer, but the specification has been released to developer community now. ºñ·Ï ¿ÃÇØ ±¸Çö¿¡¼­¸¸ 2009 ³â Â÷¼¼´ë Çٽɿ¡, BulldozerÀ¸·Î ÄÚµå¸íÁö¸¸, »ç¾ç °³¹ßÀÚ Ä¿¹Â´ÏƼ¿¡ Áö±Ý ÀÚ¸®°¡ ¸±¸®½ºµÇ¾ú½À´Ï´Ù. This has marked a meaningful milestone for AMD in the evolution for its processor architecture ahead of its competitor, Intel when defining a new standard for the community. ÀÌ ÀÚ»çÀÇ ÇÁ·Î¼¼¼­ ¾ÆÅ°ÅØÃ³¸¦ ¾ÕµÎ°í °æÀï»ç ÀÎÅÚ¿¡ ´ëÇÑ AMDÀÇ ÁøÈ­¿¡ ´ëÇÑ ÀǹÌÀÖ´Â ÀÌÁ¤Ç¥¸¦ ÇÒ ¶§ »çȸ¸¦À§ÇÑ »õ·Î¿î Ç¥ÁØÀ» Á¤ÀǷΠǥ½ÃÇß½À´Ï´Ù. If you recall, Intel has came out with SSE-SSE4 extensions instruction standard for the market since Pentium III to tackle AMD¡¯s 3D Now! ¸®ÄÝ ³²µ¿ ÇÔ²² ³ª¿Â °æ¿ì, ÀÎÅÚ - SSE4 È®Àå ¸í·É¾î Ç¥ÁØ ÆæÆ¼¾ö III ÀÌÈÄ ½ÃÀåÀº AMDÀÇ 3D ÀÌÁ¦ ÅÂŬ! capability and now AMD seems to go to release the latest version of SSE5 ahead of Intel. ÀÌÁ¦ AMD´Â ÀÎÅÚÀÇ SSE5 ´É·Â°ú ¾ÕÀ¸·ÎÀÇ ÃֽйöÀüÀ» ¸±¸®½º¿¡ °¥ °Í °°´Ù.

SSE instructions set poses a great improvement to the PC architecture performance especially when comes to power hungry processing such as graphics, multimedia and security applications. ³²µ¿ ÁöħÀ» ¼³Á¤Àº PC ¾ÆÅ°ÅØÃ³ÀÇ ¼º´ÉÀ» ƯÈ÷ ±×·¡ÇÈ, ¸ÖƼ¹Ìµð¾î ¹× º¸¾È ¾ÖÇà ¸®ÄÉÀ̼ǰú °°Àº ÇÁ·Î¼¼½Ì ÆÄ¿ö¸¦ ¿À´Â ´ë´ÜÇÑ Çâ»ó ¹è°í Æ÷Áî. However, it will be useless if there is no software development support on this feature by software vendors. ¼ÒÇÁÆ®¿þ¾î º¥´õ¿¡ ÀÇÇÑ °æ¿ì¿¡´ÂÀÌ ±â´É¿¡ ´ëÇÑ ¼ÒÇÁÆ®¿þ¾î °³¹ßÀ» Áö¿øÇÏÁö¸¸, À̰ÍÀÌ ¾µ¸ðÀÖÀ» °ÍÀÌ´Ù. Some of the great features in this SSE5 includes fused MAC (Multiply-accumulate) instruction and 3-Operand Instructions that would greatly help in multi-cores environment. ¸î °¡Áö ÁÁÀº ±â´ÉÀÌ SSE5¿¡ ÃàÀû) ¸í·É¾î ¹× 3 - Operand Áöħ¿¡ Å©°Ô µµ¿òÀÌ µÉ - ¸ÖƼ ÄÚ¾î ȯ°æ (°öÇϱâ - ¸Æ À¶ÇÕÀÌ Æ÷ÇԵǾîÀÖ½À´Ï´Ù.

Intel has not responded directly to the announcement but some may guess if Intel will adopt or decide to skip SSE5 by releasing SSE6 directly. ÀÎÅÚÀÇ Á÷Á¢ÀûÀÎ ¹ÝÀÀÀ» ¹ßÇ¥ÇÏÁö ¾Ê¾ÒÀ¸³ª ÀÎÅÚÀ» äÅÃÇÏ´Â °æ¿ì ¶Ç´Â Á÷Á¢ SSE6 °ø°³ SSE5 ¶§·ÁÄ¡ ÀϺΠÃßÃøÀÖ½À´Ï´Ù. Anyway, Penryn (Intel quad-core Xeon processor) which is about to be launched by end of this year will have the SSE4 enhancement only and hence, it would be too early to comment on this. ¾î·µç, Ææ¸° (ÀÎÅÚ Á¦¿Â ÇÁ·Î¼¼¼­ÀÇ quad - core)¿¡ ´ëÇØ¼­´Â ¿ÃÇØ ¸»±îÁö SSE4 Çâ»ó¿¡¸¸ µû¶ó¼­, ³Ê¹«ÀÌ¿¡ ´ëÇÑ ¾ð±ÞÀ» ÀÏÂï Ãâ½Ã µÉ ¿¹Á¤ÀÌ´Ù.

IMPORTANT : This is a machine translated page which is provided "as is" without warranty. Áß¿ä :ÀÌ ±â°è´Â "º¸Áõµµ¾øÀÌÀÖ´Â ±×´ë·Î"Á¦°øµË´Ï´Ù ÆäÀÌÁö¸¦ ¹ø¿ªÇß´Ù. Machine translation may be difficult to understand. ±â°è ¹ø¿ªÀ» ÀÌÇØÇϱ⠾î·Á¿ï ¼öÀÖ½À´Ï´Ù. Please refer to À» ÂüÁ¶ÇϽñ⠹ٶø´Ï´Ù original English article ¿ø·¡ ¿µ¾î ¹®¼­ whenever possible. ¾ðÁ¦µç °¡´ÉÇÕ´Ï´Ù.

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